1. Field of the Invention
The present invention generally relates to a digital loop filter suitable for a communications device that transfers digital data between a terminal device and an exchange office. More particularly, the present invention is concerned with a digital loop filter that generates phase control information necessary for a digital phase-locked loop (DPLL) circuit to synchronize, in digital form, a communications device at the user (subscriber) end having a master clock, such as a crystal oscillator, with a communications device provided at the exchange office and synchronized with a master clock signal for a network including the above communications devices.
2. Description of the Prior Art
Normally, it is required that communications devices that transfer digital data therebetween be synchronized with each other. For example, in a digital subscriber line transmission interface connecting a line terminating device provided on the exchange office side and a network terminating device provided on the user side, the line terminating device sends data to the network terminating device in synchronism with the master clock signal for the network.
FIG. 1 illustrates a PLL circuit provided in the user side. The PLL circuit is connected to a crystal oscillator OSC, and is made up of a phase comparator PC, a loop filter LF, and a frequency divider FD. Generally, a clock signal generated by the crystal oscillator OSC is out of phase with the master clock for the network. The PLL circuit functions to adjust the frequency of the clock signal generated by the crystal oscillator OSC in order to synchronize the clock signal with the master clock signal. The phase comparator PC compares the phase of a timing signal extracted from a signal sent by the office side device with the phase of a basic clock signal of the frequency divider FD, and generates a phase error information signal. The above timing signal is a repetitive frequency component.
The phase comparing operation is employed because the frequency of repetition of a data signal cannot be measured. Further, the phase of the timing signal may be different from that of the basic clock signal, even when the frequency of the timing signal is equal to that of the basic clock signal. The loop filter LF eliminates high-frequency components from the phase error signal output from the phase comparator PC. The frequency divider FD divides the frequency of the oscillator OSC in accordance with the phase error signal from the loop filter LF. In this manner, not only the phase error but also the frequency error can be corrected.
Normally, a frequency deviation of .+-.35 ppm (ppm=1/10.sup.6) of the mater clock is allowed in the digital subscriber line transmission interface. The frequency deviation of the clock signal generated by the crystal oscillator OSC is equal to .+-.100 ppm. Hence, it is necessary for the PLL circuit to cope with a frequency deviation of .+-.135 ppm.
A PLL circuit may be analog or digital. In the analog PLL circuit, a part of the capacitance of the crystal oscillator is replaced by a voltage-controlled capacitor. The frequency of the output signal of the analog PLL circuit is adjusted by varying the voltage applied to the voltage-controlled capacitor. The above analog PLL circuit can handle the .+-.135 ppm frequency deviation when the voltage-controlled capacitor has a large enough capacitance. Further, the analog PLL circuit is capable of suppressing jitter based on a deviation of the sampling timing caused during the phase control operation because the amount of variation in the capacitance per cycle can be sufficiently reduced.
However, the analog PLL circuit is expensive because it needs the voltage-controlled capacitor. In addition, the analog PLL circuit is not suitable for digital systems.
The digital PLL circuit (DPLL) circuit uses a crystal oscillator oscillating at a constant frequency. The crystal oscillator can be formed by a crystal vibrator and an inverter formed on a chip on which the circuits of the user side network terminating device are formed. The crystal vibrator and one or two capacitors are externally connected to the chip on which the inverter which is the basic circuit of the crystal oscillator is formed. Hence, the total production cost of the digital PLL circuit is less than that of the analog PLL circuit.
However, in the above case, the crystal oscillator itself cannot compensate for the .+-.100 ppm frequency deviation of the crystal vibrator. Hence, it should be said that the crystal oscillator has a frequency deviation of .+-.100 ppm.
If the crystal vibrator is mounted on the chip, the frequency deviation of the crystal vibrator can be greatly compensated for, and the frequency deviation due to other causes, such as temperature variation and deterioration with age, will be approximately .+-.50 ppm.
However, in practice, it is desirable that the digital PLL circuit can control the frequency deviation of .+-.135 ppm taking into account the worst case. The conventional DPLL circuit has a large jitter for a large frequency deviation.
The above problem will now be described. First of all, the operation of the PLL circuit shown in FIG. 1 will be described in more detail. Normally, the frequency of the master clock equal to the oscillation frequency of the crystal oscillator OSC or half thereof is selected so as to be as high as possible above the frequency of the basic clock signal equal to the baud-rate frequency at which data is received. However, there is a limit regarding the operation speed of semiconductor elements forming the oscillator, and there is also a limit regarding the frequency of the master clock signal. In the digital subscriber line transmission interface, the frequency of the basic clock signal is 80 kHz, and the frequency of the master clock signal is 15.36 MHz. Hence, the basic clock signal is obtained by dividing the master clock by 192 by means of the frequency divider FD. In other words, one pulse of the basic clock signal is generated per 192 pulses of the master clock signal.
When it is necessary to advance the phase, the loop filter LF controls the frequency divider FD so that one pulse of the basic clock signal is generated when 191 consecutive pulses of the master clock signal are counted. When it is necessary to delay the phase, the loop filter LF controls the frequency divider FD so that one pulse of the basic clock signal is generated when 193 consecutive pulses of the master clock signal are counted.
As described above, the phase control (error) information from the loop filter LF indicates that the phase is to be advanced or delayed by a constant quantity or that the phase is not to be advanced or delayed. The interval between the consecutive pulses of the basic clock signal is decreased or increased by 1/15.36 MHz (=65 ns) when the phase is advanced or delayed. The time 65 ns is equal to 1/192 times the period of the basic clock signal equal to 1/80 kHz=12500 ns. Generally, a variation in the interval between the consecutive pulses of the basic clock signal is called jitter. When the frequency of the master clock signal is 15.36 MHz and the frequency of the basic clock signal is 80 kHz, a jitter of at least .+-.1/192 (=.+-.0.005) may be caused.
The above jitter is increased due to the following causes. In the network terminating device at the user side in the digital subscriber line transmission interface, the basic clock signal is generated by dividing the frequency of the master clock signal generated by the crystal oscillator made up of crystal vibrator and the inverter formed in the LSI. Using the basic clock signal, the signal from the line terminating device at the exchange office side is received at the network terminating device. Phase information is extracted from the received signal, and is applied to the phase comparator PC.
FIG. 2 illustrates the relationship between the pre-cursor value in an isolated wave response characteristic and the timing phase. When the waveform of the received signal in the isolated wave response characteristic crosses the time axis within a threshold range around a pre-cursor value of 0, it is determined that the basic clock signal generated by the digital PLL circuit is in phase with the master clock signal for the network. In this case, the phase control is not performed. FIG. 2-(a) shows that basic clock signal is in phase with the master clock signal for the network. When the pre-cursor value has a positive value, as shown in FIG. 2-(b), it is determined that the operation timing of the network terminating device at the user side lags behind the operation timing of the line terminating device at the exchange office side. In this case, the phase of the basic timing signal is advanced. When the pre-cursor value has a negative value, as shown in FIG. 2-(c), it is determined that the operation timing of the network timing device at the user side leads that of the line terminating device at the exchange office side, and in this case the phase of the basic timing signal is delayed.
The pre-cursor value denoted as C.sub.-1 indicates the amplitude of the received signal in the isolated wave response characteristic prior, by one cycle T, to the sampling time (main cursor) at which the maximum amplitude can be obtained. The pre-cursor value can be statistically calculated by the following equation: EQU C.sub.-1 =C.sub.-1 -.alpha..multidot.sgn[e(n).multidot.a(n+1)](1)
where a(n+1) is a decision symbol value which is the output signal of a decision feedback equalizer (an adaptive equalizer), e(n) is an error, and .alpha. is a very small number called the step size.
The output signal of an adaptive equalizer as described above converges at the correct value for a long term, but it considerably deviates from the correct value for a short term. Hence, there is a possibility that it may be determined that the pre-cursor value exceeds the threshold range even though it does not exceed the threshold range. The phase control is then performed using incorrect data obtained by the statistical process, and hence jitter increases.
With the above in mind, a loop filter using an up/down counter as shown in FIG. 3 has been proposed. The loop filter shown in FIG. 3 is intended to precisely generate phase control information from phase error information obtained by using the pre-cursor value. Phase error information output from the phase comparator (not shown in FIG. 3) consists of two bits, and is applied to the up/down counter CNT. When the phase error information indicates "advance", it increments the count value of the up/down counter increments the count value of the up/down counter CNT by -1. When the phase error information indicates "in phase", it does not change the count value. When the count value of the up/down counter CNT reaches .+-.N (N is a positive integer), an overflow detection circuit ODT receiving the count value generates phase control information, and resets the up/down counter CNT. The system including the up/down counter CNT and the overflow detection circuit ODT is called random walk filter (RWF), which carries out an averaging process. As the number N increases, data averaged for a long term can be obtained, and hence the reliability of the phase control information increases.
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The network terminating device must send a 192 kHz clock signal to terminals connected thereto. There is a standard which specifies that the magnitude of jitter of the 192 kHz clock signal must be equal to or less than 5% at peak-to-peak. The 192 kHz basic clock signal can be obtained by extracting one pulse every 80 pulses of the 15.36 MHz master clock signal. When the phase control is carried out, the basic clock signal can be obtained every 79 or 81 pulses of the 15.36 MHz master clock signal. The jitter of the basic clock signal for 80.+-.1 is 2.5% at peak-to-peak. Further, the uncertainty of the phase error information is added to the 2.5% jitter. In this case, there is a large enough margin with respect to the tolerance of 5% defined in the standard. In order to reduce the uncertainty of the phase error information and satisfy the 5% tolerance, it is necessary to set the number N used in the up/down counter CNT to 128 or a similar value thereto.
However, when the number N is a large value equal to, for example, 128, the basic clock signal generated by the digital PLL circuit cannot be pulled into synchronization with the master clock signal for the network if there is a large frequency deviation. In the digital PLL circuit, there is no way to obtain synchronization other than the process for varying the interval between the consecutive pulses of the clock signal. Hence, the phase error can be corrected by varying the interval once. However, it is necessary to continuously perform the adjustment of the intervals between the consecutive pulses in order to correct the frequency deviation. The adjustment of the intervals between the consecutive pulses must be carried out more frequently as the frequency deviation increases. However, it is impossible to adjust the intervals more frequently than the number N of stages of the up/down counter CNT.
Assuming that the difference between the frequency of the clock signal in the line terminating device at the exchange office side and the frequency of the clock signal in the network terminating device at the subscriber side is Xppm, an increase in the deviation between the above clock signals for the period N=128 is obtained as follows: EQU 192.multidot.X/1000000.multidot.N
where the frequency of the master clock signal is 15.38 MHz and the frequency of the basic clock signal is 80 kHz.
When the frequency deviation is corrected by controlling the digital PLL circuit at intervals equal to N, the following equation is satisfied: EQU 192.multidot.X/1000000.multidot.N=1
Hence, the following equation is obtained: EQU N=5208.33/X (2)
When X=135 ppm, then N=38. When there is a frequency deviation of 135 ppm, it is necessary to perform the phase control every 38 pulses of the master clock signal. When N=128, only a frequency deviation equal to or less than approximately 40 ppm can be corrected.
In the case where the conventional digital PLL circuit is applied to the network terminating device in the digital subscriber line transmission interface, the standard regarding frequency deviation cannot be satisfied when the PLL circuit is designed to satisfy the standard regarding jitter. Further, the standard regarding jitter cannot be satisfied when the PLL circuit is designed to satisfy the standard regarding frequency deviation.